Quantizer circuits, sometimes referred to as “slicers”, are a type of high-speed clocked comparator which are used in serializer/deserializer (“SerDes”) and analog-to-digital conversion (“ADC”) circuits to quantize an analog signal to a digital bit. Three of the most important performance parameters of quantizers are timing measured as clock-to-q, input-referred RMS noise, and input-referred offset voltage. Input-referred RMS noise and offset voltage performance are linked by a common parameter, namely forward voltage gain, as both quantities are input-referred.
Quantizers can be broadly grouped into dynamic or static quantizers, wherein dynamic quantizers do not have any static power dissipation, and static quantizer types such as current mode logic (“CML”) quantizers do. Dynamic quantizers can be further sub-categorized into two groups, the first having what is sometimes referred to as having a STRONGARM®-type topology, sometimes referred to as a sense amplifier. The other group has what is sometimes referred to as a double-tail latch topology, which has comparatively greater sensitivity, lower input referred RMS noise and offset voltage for a given timing performance.
Dynamic quantizer timing performance is typically lowest at slow transistor process corner, high temperature and minimum supply voltage, as this process corner provides the minimum current and causes the slowest charging of the internal quantizer nodes. Input-referred RMS noise and offset voltage is typically worst at fast transistor process corner, high temperature and minimum supply voltage because that is the worst voltage gain process corner. As described herein, these process corners are referred to as the worst case timing and worst case RMS noise corners, respectively.
Previous approaches for improving input referred RMS noise and offset voltage of quantizers having the STRONGARM®-type topology have included reducing tail current, which raises the voltage gain of the quantizer. However, this reduction in tail current increases clock-to-q time of the quantizer and thus degrades timing performance. Other approaches have included increasing tail current to improve clock-to-q time of the quantizer. However, this technique reduces gain and thus impairs input referred RMS noise and offset voltage. A further approach can include increasing the input device size to increase gain rather than reducing tail current to improve input referred RMS noise and offset voltage of the quantizer. However, this causes undesirable increases in input capacitance to driving circuits and internal parasitic capacitance which also degrades timing performance.
The present disclosure provides improvements for the configuration and operation of quantizers to address these and other issues, as set forth below.